Modern electronic devices utilize semiconductor chips, commonly referred to as integrated circuits which incorporate numerous electronic elements. These chips are typically mounted on external circuit elements, such as printed circuit boards, which physically support the chips and electrically interconnect each chip with other elements of the circuit. As described in U.S. Pat. Nos. 5,148,265; 5,148,266; 5,455,390, 5,518,964 and the corresponding WO 96/02068 published Jan. 25 1996, as well as in co-pending, commonly assigned U.S. patent application Ser. Nos. 08/653,016 filed May 24, 1996; 08/678,808 filed Jul. 12, 1996 as well as 08/532,528 filed Sep. 22, 1995, the disclosures of which are all incorporated by reference herein, it may be desirable to provide interconnections between the contacts on a chip and the external circuit element by providing a flexible dielectric element having conductive terminals and flexible leads. The dielectric element is generally a flexible substrate and is typically referred to as an "interposer" or a "chip carrier." The dielectric element is preferably juxtaposed with the chip so that the chip and the dielectric element may be electrically interconnected by connecting the leads of the dielectric element to the contacts of the chip. The electrically interconnected chip and dielectric element is typically referred to as a "chip package." In turn, the terminals on the dielectric element may be connected to the external circuit element by, inter alia, solder bonding the terminals to the contact pads of the external circuit element. During operation, the dielectric element of the package remains movable with respect to the chip so as to compensate for thermal expansion and contraction of the elements. In other words, the chip can move with respect to the dielectric element as the chip grows and shrinks during changes in temperature. In a particularly preferred arrangement, a compliant dielectric layer is incorporated into the package. The compliant layer, which may be formed from a soft material such as a gel, elastomer, foam or the like, preferably lies between the chip and the terminals of the dielectric element. The compliant layer mechanically decouples the dielectric element and terminals from the chip and facilitates movement of the chip and the dielectric element relative to one another. The compliant layer may also permit movement of the terminals in the Z direction, i.e. towards the chip, which further facilitates testing and mounting of the chip package. As further disclosed in the above-mentioned patents and patent applications, one or more chips may be mounted to a common dielectric element or interposer. Alternatively, several chips may be mounted in a single package, commonly referred to as a "multichip module." These chips may be connected to one another and to a common set of external connecting elements, so that the entire chip package can be mounted to the substrate as a unit. The dielectric element may incorporate conductive traces which form interconnections between the various chips and electronic components of the package and which completes circuits as required.
The size of the chip and the chip packages is a major concern, because the size of each such package influences the overall size of the electronic device. Moreover, the size of each package controls the required distance between each of the chips within the package as well as the distance between each chip and the other elements of the circuit. Delays in transmission of electrical signals between chips, which limit the operating speed of the device, are directly related to these distances. For example, in a computer where a central processing unit operates cyclically, signals must be interchanged between the central processing unit chip and other chips during each cycle. The transmission delays inherent in such interchanges often limit the cycling rate of the central processing chip. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays, are necessary to provide for faster operation of the central processing chip.
One embodiment of the invention taught in the above-mentioned '265 Patent includes a plurality of semiconductor chip assemblies stacked one atop the other. Each individual semiconductor chip assembly includes a chip having a front contact-bearing face and a rear surface. The assembly includes an interposer overlying the front face of the chip and having central terminals which are connected to the chip contacts through conductive leads. In turn, the leads have outer extensions extending outwardly beyond the chip contacts and beyond the edges of the chip. A sheet-like backing element having conductive terminals on a surface thereof abuts the rear face of chip, so that the chip is sandwiched between the backing element and the interposer. A plurality of the above-described chip assemblies are combined to form a larger, multichip circuit assembly, whereby the chip assemblies are electrically interconnected and stacked one atop the other, with the backing element of each chip assembly overlying the interposer of the next lower chip assembly.
Commonly assigned U.S. Pat. No. 5,347,159, the disclosure of which is hereby incorporated by reference herein, also discloses a stacked chip assembly including a plurality of semiconductor chips which are stacked one atop the other and electrically interconnected. In one embodiment, a stacked chip assembly includes three chips: a top chip, an intermediate chip and a bottom chip. The chips are electrically interconnected with one another and the assembly is electrically connected to an external circuit element.
The stacked circuit assemblies or multichip packages shown and described in the '265 and '159 Patents are particularly useful for accommodating large numbers of chips in a small area. The chips are stacked in essentially the same circuit board area as ordinarily occupied by a single chip. These stacked packages are especially useful with memory chips such as random access memory chips, whereby the chips are provided with parallel connections to a data bus.
However, still further improvements in chip assemblies and in the methods utilized to make the same would be desirable.